Modern data centers are being transformed to meet the increased processing needs of specialized workloads with an advantageous total cost of ownership. To this end, the modular design of current microservers allows the inclusion of heterogeneous computing platforms and accelerators to enhance the performance of specific workloads, while improving the power consumption and maintenance costs of the whole system. One of the fundamental application domains for datacenters is represented by bulk data encryption and decryption, as it has to be performed on the data being stored as well as on data being transmitted or received. In this paper we investigate the OpenCL programming practices to realize high-performance FPGA accelerators, thus providing a viable and more versatile alternative to the use of ad-hoc cryptographic accelerators, which are currently available in high-end server CPUs only. We validate our analysis employing AES-128 as our case study, and report energy efficiency improvements of 22.78 times with respect to pure software implementations of ISO standard block ciphers.

OpenCL HLS Based Design of FPGA Accelerators for Cryptographic Primitives

A. Barenghi;N. Mainardi;G. Pelosi
2018-01-01

Abstract

Modern data centers are being transformed to meet the increased processing needs of specialized workloads with an advantageous total cost of ownership. To this end, the modular design of current microservers allows the inclusion of heterogeneous computing platforms and accelerators to enhance the performance of specific workloads, while improving the power consumption and maintenance costs of the whole system. One of the fundamental application domains for datacenters is represented by bulk data encryption and decryption, as it has to be performed on the data being stored as well as on data being transmitted or received. In this paper we investigate the OpenCL programming practices to realize high-performance FPGA accelerators, thus providing a viable and more versatile alternative to the use of ad-hoc cryptographic accelerators, which are currently available in high-end server CPUs only. We validate our analysis employing AES-128 as our case study, and report energy efficiency improvements of 22.78 times with respect to pure software implementations of ISO standard block ciphers.
2018
Proceedings - 2018 International Conference on High Performance Computing and Simulation, HPCS 2018
978-153867878-7
OpenCL, High-throughput Cryptographic Implementations, High Level Synthesis, Electronic System-level Synthesis, FPGA, Programming practices
File in questo prodotto:
File Dimensione Formato  
main.pdf

Accesso riservato

Descrizione: main article
: Post-Print (DRAFT o Author’s Accepted Manuscript-AAM)
Dimensione 249.3 kB
Formato Adobe PDF
249.3 kB Adobe PDF   Visualizza/Apri
main.pdf

accesso aperto

Descrizione: Pre-print version of the article
Dimensione 195.66 kB
Formato Adobe PDF
195.66 kB Adobe PDF Visualizza/Apri

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1070245
Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 3
  • ???jsp.display-item.citation.isi??? 2
social impact