This paper discusses the most recent advances in the design of fast chirp modulators in modern CMOS processes for FMCW radar applications. Saw-tooth chirps with large amplitude and short repetition period are needed to achieve at the same time tight spatial resolution and large duty cycle, but they require an extremely fast frequency modulator. The direct-FM modulation of a fractional-N phase-locked loop does not allow to reach such values. To solve this issue, digital PLLs have been investigating in these years, combined with two main speed-enhancement techniques, namely the signal pre- emphasis and the two-point injection. A 65-nm CMOS chirp modulator is fabricated, which adopts an innovative digital PLL topology with two-point injection and automatic pre- distortion of the modulation signal. The digital circuitry tracks and compensates in the background for process and environmental variations. The modulator is capable to generate a saw-tooth chirp signal with up to 416MHz peak-to-peak amplitude around 22GHz, with repetition period down to 1.2μs and idle time of 140ns. The measured phase noise is -101dBc/Hz at 1MHz offset and the power consumption is about 19.7mW.

Digitally-Assisted Frequency Synthesizers for Fast Chirp Generation in mm-Wave radars

S. Levantino;C. Samori
2018

Abstract

This paper discusses the most recent advances in the design of fast chirp modulators in modern CMOS processes for FMCW radar applications. Saw-tooth chirps with large amplitude and short repetition period are needed to achieve at the same time tight spatial resolution and large duty cycle, but they require an extremely fast frequency modulator. The direct-FM modulation of a fractional-N phase-locked loop does not allow to reach such values. To solve this issue, digital PLLs have been investigating in these years, combined with two main speed-enhancement techniques, namely the signal pre- emphasis and the two-point injection. A 65-nm CMOS chirp modulator is fabricated, which adopts an innovative digital PLL topology with two-point injection and automatic pre- distortion of the modulation signal. The digital circuitry tracks and compensates in the background for process and environmental variations. The modulator is capable to generate a saw-tooth chirp signal with up to 416MHz peak-to-peak amplitude around 22GHz, with repetition period down to 1.2μs and idle time of 140ns. The measured phase noise is -101dBc/Hz at 1MHz offset and the power consumption is about 19.7mW.
19th International Radar Symposium (IRS)
9783736995451
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/1065364
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