Time-resolved experiments often need detection devices able to provide information about position and arrival time of each detected event. Time resolution is a fundamental requirement for these devices, along with the high versatility and fast real-time computing of the acquisition system. Typical architectures, based on Time-to-Digital Converters (TDC) followed by a FPGA, combine very fast parallel computing with a time precision better than hundreds of picoseconds, allowing to perform state-of-the-art time-resolved experiments. Nevertheless, time resolution is still a limiting factor, in particular for imaging applications where the detector spatial resolution is determined through time measurement. Furthermore, the separation between the TDC devices and a readout FPGA has some drawbacks in terms of versatility of the system. In this article, we present a new approach, combining FPGA-based multi-channel Tapped-Delay-Line TDC and an efficient multipurpose readout logic, to greatly improve the overall performance and versatility of Cross Delay-Line (CDL) detector systems.

Development of Fully FPGA-based 3D (X, Y, t) Detection Systems using Multi-channel Tapped Delay-Line Time-to-Digital Converter with Cross Delay-Line Detectors

N. Lusardi;F. Garzetti;A. Geraci
2017-01-01

Abstract

Time-resolved experiments often need detection devices able to provide information about position and arrival time of each detected event. Time resolution is a fundamental requirement for these devices, along with the high versatility and fast real-time computing of the acquisition system. Typical architectures, based on Time-to-Digital Converters (TDC) followed by a FPGA, combine very fast parallel computing with a time precision better than hundreds of picoseconds, allowing to perform state-of-the-art time-resolved experiments. Nevertheless, time resolution is still a limiting factor, in particular for imaging applications where the detector spatial resolution is determined through time measurement. Furthermore, the separation between the TDC devices and a readout FPGA has some drawbacks in terms of versatility of the system. In this article, we present a new approach, combining FPGA-based multi-channel Tapped-Delay-Line TDC and an efficient multipurpose readout logic, to greatly improve the overall performance and versatility of Cross Delay-Line (CDL) detector systems.
2017
IEEE Transactions on Nuclear Science ( Volume: 64, Issue: 9, Sept. 2017 )
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1063806
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