In today’s fractional-N phase-locked loops, digital- to-time converters are commonly used to cancel the quantization noise of the divider modulus, and a least-mean squares loop is used to adapt the gain of the cancellation path. Unfortunately, a trade-off exists between the time range needed to the digital-to- time converter and the speed of convergence of the calibration. In this paper, a novel scheme significantly relaxing this trade-off and allowing for a low-power implementation of both the digital- to-time converter and the calibration loop, is introduced. The effectiveness of the proposed concept is verified via behavioral simulations in the presence of circuits non-idealities, showing a reduction of at a least a factor of 5x in the settling time of the calibrated coefficient.

A Novel LMS-Based Calibration Scheme for Fractional-N Digital PLLs

Vo, Tuan Minh;Samori, Carlo;Levantino, Salvatore
2018

Abstract

In today’s fractional-N phase-locked loops, digital- to-time converters are commonly used to cancel the quantization noise of the divider modulus, and a least-mean squares loop is used to adapt the gain of the cancellation path. Unfortunately, a trade-off exists between the time range needed to the digital-to- time converter and the speed of convergence of the calibration. In this paper, a novel scheme significantly relaxing this trade-off and allowing for a low-power implementation of both the digital- to-time converter and the calibration loop, is introduced. The effectiveness of the proposed concept is verified via behavioral simulations in the presence of circuits non-idealities, showing a reduction of at a least a factor of 5x in the settling time of the calibrated coefficient.
2018 IEEE International Symposium on Circuits and Systems (ISCAS)
978-1-5386-4881-0
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/1055421
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