This paper discusses the impact of CMOS scaling in the design and performance of switched-capacitor power amplifiers operating in the sub-GHz bands for Internet-of-Things applications. While the peak drain efficiency is found to improve by about 10% when the amplifier is scaled down from a 65-nm standard CMOS to a 28-nm fully-depleted SOI CMOS process, the average efficiency instead slightly degrades. Moreover, it is theoretically demonstrated that the power density (peak-power over area-occupation) is a function of the supply voltage and the dielectric constant of the switched capacitor insulator, and it is about 13% higher in the 65-nm CMOS node.

Impact of CMOS Scaling on Switched-Capacitor Power Amplifiers

TRUPPI, ALESSANDRO;Samori, Carlo;Lacaita, Andrea L.;Levantino, Salvatore;
2018

Abstract

This paper discusses the impact of CMOS scaling in the design and performance of switched-capacitor power amplifiers operating in the sub-GHz bands for Internet-of-Things applications. While the peak drain efficiency is found to improve by about 10% when the amplifier is scaled down from a 65-nm standard CMOS to a 28-nm fully-depleted SOI CMOS process, the average efficiency instead slightly degrades. Moreover, it is theoretically demonstrated that the power density (peak-power over area-occupation) is a function of the supply voltage and the dielectric constant of the switched capacitor insulator, and it is about 13% higher in the 65-nm CMOS node.
2018 IEEE International Symposium on Circuits and Systems (ISCAS)
978-1-5386-4881-0
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/1055419
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