The need for low-noise, highly-linear, programmable chirp generators makes digital phase-locked loops (DPLLs) an attractive solution for radar sensors. This paper presents a general analysis and comparison of the two main techniques enabling wideband frequency modulation (FM) in PLLs, namely the two-point injection and the pre-emphasis. It is shown that while the two topologies are equivalent in term of mismatch error suppression, the required input range for the time-to-digital converter (TDC) is substantially lower in the two-point injection scheme, thus relaxing the TDC power consumption and linearity.

A novel segmentation scheme for DTC-based ΔΣ fractional-N PLL

VO, TUAN MINH;SAMORI, CARLO;LACAITA, ANDREA LEONARDO;LEVANTINO, SALVATORE
2017-01-01

Abstract

The need for low-noise, highly-linear, programmable chirp generators makes digital phase-locked loops (DPLLs) an attractive solution for radar sensors. This paper presents a general analysis and comparison of the two main techniques enabling wideband frequency modulation (FM) in PLLs, namely the two-point injection and the pre-emphasis. It is shown that while the two topologies are equivalent in term of mismatch error suppression, the required input range for the time-to-digital converter (TDC) is substantially lower in the two-point injection scheme, thus relaxing the TDC power consumption and linearity.
2017
2017 IEEE International Symposium on Circuits and Systems (ISCAS)
978-1-4673-6853-7
sezele, CMOS, PLL, TDC, digital PLL
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1032793
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