Testability analysis can be performed through classification of all possible simple interconnection topologies, definition of testability conditions on the functions performed by the cells composing the circuit and identification of the composition rules of such interconnections and of the testability conditions determined. This approach works well whenever feed-forward architectures are studied. Application of such approach to irregular architectures with cycles (signal feedbacks) is presented in this paper.
Reduction of fault detection costs through testable design of sequential architectures with signal feedbacks
FERRANDI, FABRIZIO;SCIUTO, DONATELLA;
1993-01-01
Abstract
Testability analysis can be performed through classification of all possible simple interconnection topologies, definition of testability conditions on the functions performed by the cells composing the circuit and identification of the composition rules of such interconnections and of the testability conditions determined. This approach works well whenever feed-forward architectures are studied. Application of such approach to irregular architectures with cycles (signal feedbacks) is presented in this paper.File in questo prodotto:
Non ci sono file associati a questo prodotto.
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.