On the automation of high level synthesis of convolutional neural networks

Convolutional Neural Networks (CNNs) are a particular type of Artificial Neural Networks (ANNs) inspired by cells in the primary visual cortex of animals, and represent the state of the art in image recognition and classification. Nowadays, such supervised learning technique is very popular in Big Data analytics. In this context, due to the huge amount of data to be processed, it is crucial to find techniques to speed up the computation. In particular, the dataflow pattern of CNN algorithm results to be suitable for hardware acceleration. This paper proposes a framework to automatically generate a hardware implementation of CNNs on Field Programmable Gate Arrays (FPGAs), based on the High Level Synthesis (HLS) of configurable offline-trained networks.