Behavioral test generation for the selection of BIST logic

The identification of the most suited BIST architecture is one of the bottlenecks in the actual application of self-testing techniques. The aim of this paper is the investigation of possible relations between the behavioral level specification of the circuit, and the structural level, where BIST logic is inserted. We propose to use behavioral test patterns to guide the selection of the most appropriate BIST architecture with respect to the given application as a trade-off between fault coverage and area overhead. The correlation between the behavioral analysis and the actual fault coverage of the inserted BIST logic has been shown on a number of benchmarks.