RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

DISTANTE, FAUSTO
 Distribuzione geografica
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Continente #
NA - Nord America 1.170
EU - Europa 475
AS - Asia 110
AF - Africa 8
Continente sconosciuto - Info sul continente non disponibili 1
Totale 1.764
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Nazione #
US - Stati Uniti d'America 1.155
AT - Austria 106
UA - Ucraina 99
IT - Italia 71
DE - Germania 65
SG - Singapore 43
FI - Finlandia 38
SE - Svezia 34
VN - Vietnam 34
CN - Cina 20
ES - Italia 17
CA - Canada 15
GB - Regno Unito 13
IE - Irlanda 11
NL - Olanda 9
IN - India 8
CI - Costa d'Avorio 7
CZ - Repubblica Ceca 6
BE - Belgio 4
FR - Francia 2
TR - Turchia 2
A1 - Anonimo 1
BJ - Benin 1
JO - Giordania 1
JP - Giappone 1
KR - Corea 1
Totale 1.764
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Città #
Ann Arbor 125
Chandler 125
Woodbridge 120
Fairfield 111
Vienna 106
Ashburn 87
Wilmington 79
Santa Clara 66
Houston 55
Jacksonville 54
Seattle 48
Singapore 30
Cambridge 25
Dearborn 24
Boardman 21
Lawrence 21
Helsinki 17
Medford 17
Málaga 17
New York 16
Dong Ket 15
Beijing 14
Ottawa 14
Dublin 11
Amsterdam 8
Abidjan 7
Des Moines 7
Brno 6
San Diego 6
Washington 5
Brussels 4
Falls Church 4
Milan 4
Princeton 4
Frankfurt am Main 3
Norwalk 3
Redwood City 3
Hanover 2
Hefei 2
Izmir 2
Mountain View 2
Parma 2
Vittuone 2
Amman 1
Auburn Hills 1
Berlin 1
Cotonou 1
Denver 1
Falkenstein 1
Gavirate 1
Gunzenhausen 1
Kumar 1
Kunming 1
London 1
Nanjing 1
Newcastle upon Tyne 1
Ningbo 1
Nürnberg 1
Rome 1
San Francisco 1
San Giovanni La Punta 1
Shanghai 1
Tokyo 1
Toronto 1
Varese 1
Verona 1
Totale 1.317
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Nome #
Array partitioning: a methodology for reconfigurability and reconfiguration problems 168
Area compaction in Silicon Structures for Neural Net Implementation 108
APES - Implementation of a CAD tool for array processor design: Textual definition versus graphic description 108
A Compact and Fast Silicon Implementation for Layered Neural Nets 107
Fault Tolerant Characteristics of the Linear Array Architecture for WSI Implementation of Neural Nets 106
High level synthesis through folding of data flow graphs: optimal intra-node scheduling 104
A configurable array architecture for WSI implementation of neural nets 101
Testing of Very Large Systems - A Hierarchical Approach To Fault Coverage Evaluation 100
A general configurable architecture for WSI implementation for neural nets 95
A digital Architecture for Neural Networks 87
High level architectural synthesis: precedence analysis ad automatic cycle detection 84
Multistage Interleaved Architectures for Implementation of Neural Networks 78
A Proposal for Neural Macrocell Array 74
Fault Tollerant Aspects in Silicon Structures for Neural Nets 69
An Approach for Digital Neural Network Design 66
DFGs for Synthesis of Alternatives Architectures: Node Activation Synthesis 66
A semi-custom approach for digital implementation of neural networks 63
Alternative Approaches for Mapping Neural Networks onto Silicon 61
Optimal Balancing of Acyclic and Cyclic Data Flow Graphs in High Level Architectural Synthesis 52
Mapping Neural Nets onto Massively parallel Silicon Architectures: A Defect-Tolerance Solution 51
An Array Architecture for WSI Implementation of Neural Nets 51
Totale 1.799
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Categoria #
all - tutte 5.403
article - articoli 1.979
book - libri 0
conference - conferenze 3.424
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 0
Totale 10.806
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/2020198 0 0 0 0 0 26 46 19 45 14 42 6
2020/2021196 21 5 23 3 25 6 19 20 11 20 7 36
2021/2022162 10 14 5 5 39 5 8 6 4 13 13 40
2022/2023271 43 34 7 18 31 27 0 25 40 26 19 1
2023/2024152 10 21 6 18 9 30 8 2 2 22 0 24
2024/2025136 3 14 14 1 104 0 0 0 0 0 0 0
Totale 1.799