This paper presents a first prototype of a 12-bit analog-to-digital converter (ADC) suitable for X and γ-ray multichannel readout front-ends for SDD signals processing. The task of the converter is the digitization of output multiplexed data at a sampling frequency up to 5 MS/s and about 11-bit accuracy. The chosen architecture is the fully-differential bridge-capacitor charge-redistribution (CR) successive-approximation-register (SAR) with monotonic switching algorithm. The chip is fabricated in a standard CMOS 0.35 μm 3.3 V technology and the ADC area occupancy is 0.42 mm2. The measured input-output characteristic shows monotonicity over the whole dynamic range while static parameters are -0.17/1.22 LSB and -2.2/2.2 LSB respectively for differential (DNL) and integral nonlinearity (INL). Dynamic performance consist in 68 dB SFDR, 66.5 dB SiNAD and an effective number of bits (ENOB) equal to 10.75 at 4 MS/s. An in-depth analysis of the circuit topology together with simulated and experimental results are here presented.

A 12-bit charge-redistribution SAR ADC for silicon drift detector readout ASICs

SCHEMBARI, FILIPPO;QUAGLIA, RICCARDO;ABBA, ANDREA;CAPONIO, FRANCESCO;FIORINI, CARLO ETTORE
2014

Abstract

This paper presents a first prototype of a 12-bit analog-to-digital converter (ADC) suitable for X and γ-ray multichannel readout front-ends for SDD signals processing. The task of the converter is the digitization of output multiplexed data at a sampling frequency up to 5 MS/s and about 11-bit accuracy. The chosen architecture is the fully-differential bridge-capacitor charge-redistribution (CR) successive-approximation-register (SAR) with monotonic switching algorithm. The chip is fabricated in a standard CMOS 0.35 μm 3.3 V technology and the ADC area occupancy is 0.42 mm2. The measured input-output characteristic shows monotonicity over the whole dynamic range while static parameters are -0.17/1.22 LSB and -2.2/2.2 LSB respectively for differential (DNL) and integral nonlinearity (INL). Dynamic performance consist in 68 dB SFDR, 66.5 dB SiNAD and an effective number of bits (ENOB) equal to 10.75 at 4 MS/s. An in-depth analysis of the circuit topology together with simulated and experimental results are here presented.
2014 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC)
978-1-4799-6097-2
978-1-4799-6097-2
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/987522
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