The DSSC collaboration is developing an instrument for the detection of synchrotron X-rays (E >; 0.5 keV) at XFEL. The hexagonal pixels of a DEPFET based sensor with integrated signal compression will be read out by bump-bonded pixel readout ASICs. Each ASIC will have 64 × 64 pixel channels of 236 × 204 μm2 area, each one containing a low-noise (<; 50 e-) amplification of the DEPFET signal, an 8 bit single-slope ADC and a digital memory, as well as other blocks for test injection, gain switching and trimming. Data is acquired during the XFEL burst at a rate of up to 4.5 MHz. The signal is first processed by a trapezoidal shaping filter, digitized immediately and then stored to the in-pixel memory of >; 512 events capacity. The accumulated digital data is transferred off chip during the 100 ms long burst gaps on a single serial link while the analogue sections are shut down to bring the average power dissipation to <; 100 mW per ASIC. The chip architecture is described and results obtained from first test chips are presented.

Pixel readout ASIC with per pixel digitization and digital storage for the DSSC detector at XFEL

BOMBELLI, LUCA;FACCHINETTI, STEFANO;FIORINI, CARLO ETTORE;PORRO, MATTEO;
2010

Abstract

The DSSC collaboration is developing an instrument for the detection of synchrotron X-rays (E >; 0.5 keV) at XFEL. The hexagonal pixels of a DEPFET based sensor with integrated signal compression will be read out by bump-bonded pixel readout ASICs. Each ASIC will have 64 × 64 pixel channels of 236 × 204 μm2 area, each one containing a low-noise (<; 50 e-) amplification of the DEPFET signal, an 8 bit single-slope ADC and a digital memory, as well as other blocks for test injection, gain switching and trimming. Data is acquired during the XFEL burst at a rate of up to 4.5 MHz. The signal is first processed by a trapezoidal shaping filter, digitized immediately and then stored to the in-pixel memory of >; 512 events capacity. The accumulated digital data is transferred off chip during the 100 ms long burst gaps on a single serial link while the analogue sections are shut down to bring the average power dissipation to <; 100 mW per ASIC. The chip architecture is described and results obtained from first test chips are presented.
Nuclear Science Symposium Conference Record (NSS/MIC), 2010 IEEE
9781424491049
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/766010
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