We present a compact TDC Module based on the Time-to-Digital Converter ASIC fabricated in 0.35 μm CMOS technology. This chip measures the time-interval between two inputs, called START and STOP, with a 10 ps resolution when using a 10 ns reference clock. Thanks to the structure, composed by two independent “interpolators” for each input and a “coarse” counter, the TDC chip can reach an average precision better than 15 psRMS and a differential non-linearity (DNL) smaller than 0.9 %LSB with a maximum conversion rate of about 3 Msps. A simple calibration allows to compute proper coefficients to apply to raw data. The TDC Module is composed by two SMA inputs, followed by an electronic front-end to provide compatibility to any kind of signal, an USB 2.0 connector for parameters setting and data upload to a remote computer and the power supply connector.

TDC with 1.5% DNL based on a single-stage vernier delay-loop fine interpolation

TAMBORINI, DAVIDE;MARKOVIC, BOJAN;TISA, SIMONE;VILLA, FEDERICA ALBERTA;TOSI, ALBERTO
2013

Abstract

We present a compact TDC Module based on the Time-to-Digital Converter ASIC fabricated in 0.35 μm CMOS technology. This chip measures the time-interval between two inputs, called START and STOP, with a 10 ps resolution when using a 10 ns reference clock. Thanks to the structure, composed by two independent “interpolators” for each input and a “coarse” counter, the TDC chip can reach an average precision better than 15 psRMS and a differential non-linearity (DNL) smaller than 0.9 %LSB with a maximum conversion rate of about 3 Msps. A simple calibration allows to compute proper coefficients to apply to raw data. The TDC Module is composed by two SMA inputs, followed by an electronic front-end to provide compatibility to any kind of signal, an USB 2.0 connector for parameters setting and data upload to a remote computer and the power supply connector.
Time-to-Digital Converters (NoMe TDC), 2013 IEEE Nordic-Mediterranean Workshop on
978-147991184-4
sezele
File in questo prodotto:
File Dimensione Formato  
2013 - Tamborini - TDC with 1.5 % DNL based on a Single-Stage Vernier Delay-Loop Fine Interpolation.pdf

Accesso riservato

: Post-Print (DRAFT o Author’s Accepted Manuscript-AAM)
Dimensione 1.96 MB
Formato Adobe PDF
1.96 MB Adobe PDF   Visualizza/Apri

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/760702
Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 1
  • ???jsp.display-item.citation.isi??? ND
social impact