Configuration-specific test pattern extraction for field programmable gate arrays

The aim of this paper is to present a methodology for extracting configuration-specific test patterns for FPGA cells, from the set of sequences that test all stuck-at-faults for the unconfigured cell. This is achieved through the construction of an automaton that recognises test sequences for all faults, followed by the extraction of a second automaton that recognises only the non-redundant faults with respect to a given configuration. Since structural information is not needed for sequence extraction, this methodology provides the user with a structural fault model while granting protection of Intellectual Property