Modern multi-core architectures are prone to a complex dynamic thermal management process: the presence of multiple cores adds challenges to the temperature estimation activity, due to the induced heat-up process from adjacent cores. Run-time estimation can benefit from floorplan information to better estimate the thermal characteristics of each core, and transient information can help the system to predict and avoid thermal alarms, increasing the system reliability and lifetime. In this context, the present work aims at defining a novel on-line measurement methodology based on neighbor nodes and transient information, providing a metric to be employed in thermal-aware designs, either at design-time to characterize application and platform from a thermal view-point, or at run-time in conjunction with the Dynamic Thermal Management subsystem. The proposed methodology intercepts floorplan-induced thermal behavior that would be otherwise unrecognized, and it also shows how a non-floorplan-aware methodology can reveal up to a 30% error in the estimate of thermal status.

Estimation of thermal status in multi-core systems

CORBETTA, SIMONE;FORNACIARI, WILLIAM
2011-01-01

Abstract

Modern multi-core architectures are prone to a complex dynamic thermal management process: the presence of multiple cores adds challenges to the temperature estimation activity, due to the induced heat-up process from adjacent cores. Run-time estimation can benefit from floorplan information to better estimate the thermal characteristics of each core, and transient information can help the system to predict and avoid thermal alarms, increasing the system reliability and lifetime. In this context, the present work aims at defining a novel on-line measurement methodology based on neighbor nodes and transient information, providing a metric to be employed in thermal-aware designs, either at design-time to characterize application and platform from a thermal view-point, or at run-time in conjunction with the Dynamic Thermal Management subsystem. The proposed methodology intercepts floorplan-induced thermal behavior that would be otherwise unrecognized, and it also shows how a non-floorplan-aware methodology can reveal up to a 30% error in the estimate of thermal status.
2011
Proceeding of 2011 IEEE International Symposium of Circuits and Systems (ISCAS)
978-1-4244-9473-6
978-1-4244-9474-3
978-1-4244-9472-9
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/608291
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