We present an integrated analog front-end for the readout of a non-linear DEPFET Sensor with Signal Compression (DSSC). The DSSC system, currently under development, is a 1-Mega pixel detector system for the European X-ray Free Electron Laser (XFEL) in Hamburg. It will record Xray images with a maximum frame rate of 4.5MHz and will achieve at the same time a single photon resolution at 1keV and a high dynamic range. Two different readout strategies of the DEPFET pixel, Source Follower (SF) and Drain Readout (DR), have been fabricated in the 1.2V 0.13μm IBM CMOS technology. Both solutions share the same analog filter based on a new architecture that implements a trapezoidal shaping function employing only one operational amplifier. In this paper, the architecture of the analog front-end relative to both the readout strategies and of the new designed filter and the performance of the test chips are presented.

A 5MHz Low-Noise 130nm CMOS Analog Front-End Electronics for the Readout of Non-Linear DEPFET Sensor with Signal Compression for the European XFEL

BOMBELLI, LUCA;PORRO, MATTEO;FACCHINETTI, STEFANO;FIORINI, CARLO ETTORE;
2010

Abstract

We present an integrated analog front-end for the readout of a non-linear DEPFET Sensor with Signal Compression (DSSC). The DSSC system, currently under development, is a 1-Mega pixel detector system for the European X-ray Free Electron Laser (XFEL) in Hamburg. It will record Xray images with a maximum frame rate of 4.5MHz and will achieve at the same time a single photon resolution at 1keV and a high dynamic range. Two different readout strategies of the DEPFET pixel, Source Follower (SF) and Drain Readout (DR), have been fabricated in the 1.2V 0.13μm IBM CMOS technology. Both solutions share the same analog filter based on a new architecture that implements a trapezoidal shaping function employing only one operational amplifier. In this paper, the architecture of the analog front-end relative to both the readout strategies and of the new designed filter and the performance of the test chips are presented.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/574374
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