The optimization of the noise performance of integrated CMOS charge amplifiers is studied in detail considering accurate 1/f noise modeling for the input MOSFET biased in strong inversion-saturation region. This work aims to generalize and correct previously published analyses which have been based on two limiting and sometimes not applicable assumptions: a fixed MOSFETs bias current and the general validity of the McWhorter 1/f noise model. This study considers the two main 1/f noise models: 1) the mobility fluctuation, known as Du or Hooge model, which is followed by p-channel MOSFETs and 2) the carriers number fluctuation, also known as DN or McWhorter model, which is applicable only for n channel MOSFETs. The front-end noise optimization is made with the 1/f component alone, thus determining the ultimate performance, and also considering the presence of series and parallel white noise sources. It is shown that different design criteria are valid of p- or n-channel MOSFETs: the Du model results in an optimum bias current and a different optimum gate with respect to DN model. Two-dimensions sub-optimum noise minimization criteria are derived when power or area constraints are imposed to the circuit design. Starting from experimental data on CMOS 1/f noise, examples of application of the presented analysis are shown to predict the lower limits of the 1/f noise contribution for the currently available CMOS technologies.
Noise Minimization of MOSFET Input Charge Amplifier based on Du and DN 1/f Models
BERTUCCIO, GIUSEPPE;CACCIA, STEFANO
2009-01-01
Abstract
The optimization of the noise performance of integrated CMOS charge amplifiers is studied in detail considering accurate 1/f noise modeling for the input MOSFET biased in strong inversion-saturation region. This work aims to generalize and correct previously published analyses which have been based on two limiting and sometimes not applicable assumptions: a fixed MOSFETs bias current and the general validity of the McWhorter 1/f noise model. This study considers the two main 1/f noise models: 1) the mobility fluctuation, known as Du or Hooge model, which is followed by p-channel MOSFETs and 2) the carriers number fluctuation, also known as DN or McWhorter model, which is applicable only for n channel MOSFETs. The front-end noise optimization is made with the 1/f component alone, thus determining the ultimate performance, and also considering the presence of series and parallel white noise sources. It is shown that different design criteria are valid of p- or n-channel MOSFETs: the Du model results in an optimum bias current and a different optimum gate with respect to DN model. Two-dimensions sub-optimum noise minimization criteria are derived when power or area constraints are imposed to the circuit design. Starting from experimental data on CMOS 1/f noise, examples of application of the presented analysis are shown to predict the lower limits of the 1/f noise contribution for the currently available CMOS technologies.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
