Automatic Thermal Network Extraction and Multiscale Electro-Thermal Simulation

We present a new strategy to perform chip-level electro-thermal simulation. In our approach electrical behaviour of each circuit element is modeled by standard compact models with an added temperature node (1; 2). Mutual heating is accounted for by a 2-D or 3-D diffusion reaction PDE, which is coupled to the electrical network by enforcing instantaneous energy conservation. To cope with the multiscale nature of heat diffusion in VLSI circuit a suitable spatial discretization scheme is adopted which allows for efficient meshing of large domains with details at a much smaller scale. Preliminary numerical results on a realistic test case are included as a validation of the model and of the numerical method.