Innovative packaging technique for backside optical testing of wire-bonded chips

This paper describes an innovative packaging technique for versatile backside optically testing chips that require wire bonding. Since both electrical connections to the device under test and optical access through the silicon substrate are required, the sample preparation for testing the chip becomes a key issue. In fact, the thinned die is very fragile and a specific holder is necessary. The proposed package fulfils all these requirements and can be used for PICA measurements, EMMI investigations, LVP, TLS, PLS and other failure analysis methods that require optical access to the transistor level through the silicon backside.