Innovative packaging technique for Backside optical testing of wire-bonded chips

This paper describes an innovative packaging technique for versatile backside optically testing chips that require wire bonding. Both electrical connections to the device under test and optical access through the silicon substrate are required. Therefore the sample preparation for testing a chip is a key issue. In fact, the thinned die is very fragile and a specific holder is necessary. The proposed package fulfils all those requirements and it can be used for PICA-like techniques, EMMI investigations, LVP, TLS, PLS and other analysis methods that require optical access to the transistor level through the silicon backside.