Reality Check for RISC-V: Assessing Software Maturity, Performance and Security

The open and modular nature of the RISC-V Instruction Set Architecture (ISA) has produced a fragmented landscape of hardware implementations and software environments, with direct consequences on portability, performance, and resilience to hardware attacks. The practical maturity of its most prominent cores, however, is rarely assessed in a unified manner and on real hardware rather than in simulation. This paper presents such an evaluation for six representative cores: three commercial ASICs (SiFive P550, Orange Pi RV2, Microchip PIC64GX) and three configurable FPGA-based soft-cores (BOOM, NOEL-V, CVA6). We study them along three complementary axes, namely the maturity of their software environments, distilled from hands-on deployment; their computational performance, measured with CoreMark, Geekbench 6, and SPEC2017 and contextualised against ARM and x86 cores; and the susceptibility of the open-source soft-cores to a comprehensive set of Transient Execution Attacks (TEAs). Our results identify the SiFive P550 as the strongest performer, comparable with mid-range embedded ARM cores but well behind high-end ARM and x86 designs; they show that the tested soft-core deployments are not yet ready for complex general-purpose workloads; and they reveal that even in-order cores are vulnerable to TEAs, with distinct profiles tied to their microarchitectures.