An experimental evaluation of RISC-V cores: Software support and performance analysis

Although the RISC-V Instruction Set Architecture (ISA) offers an open-standard alternative to proprietary models, the practical maturity of the most famous commercially available cores and the real-world challenges associated with their deployment have not been fully explored yet. Indeed, the open-source nature of such ISA has led to a fragmented landscape of hardware implementations and software environments, thus creating significant integration challenges for developers. This paper provides an experimental evaluation of a representative set of RISC-V cores based on the practical use of real hardware implementations, moving beyond theoretical/simulative assessments to deliver detailed insights grounded in direct experience. Our analyses have been conducted on six prominent RISC-V cores, including three commercial ASIC implementations, namely the SiFive P550, the Orange Pi RV2 and the Microchip PIC64GX, and three configurable FPGA-based soft-cores, namely BOOM, CVA6 and Noel-V. We first report a qualitative analysis of the maturity and usability of the software environments associated with the considered cores, distilled from our hands-on deployment experience, and we then measure the computational performance by means of the CoreMark, Geekbench 6, and SPEC2017 benchmark suites. Our results highlight the SiFive P550 as the top-performance core among the ones we considered while they suggest that the tested deployments of the considered FPGA-based soft-cores are not yet stable enough for complex, general-purpose workloads in the current deployable form. Moreover, a comparative analysis against alternative core architectures reveals that the performance achieved by the best-performing RISC-V ASIC of our set is comparable with the performance of established mid-range embedded ARM cores while a significant performance gap still exists w.r.t. high-end ARM and x86 cores.