FPGA-Based Reset Management for Multiple Parallelized Readout ASICs Connected to a Multi-Cell SDD

For X-ray imaging and photon detection, silicon drift detectors (SDDs) with several cells on a single chip and associated application-specific integrated circuits (ASICs) with multi-channel readout are widely used. This work presents a reset management circuit for a parallelized readout system for multi-cell SDDs. The readout system under investigation consists of a 19-cell SDD chip and three ASICs with reset capabilities. Yet, another reset management circuit is required, which handles the seamless reset operation between all ASICs and the SDD chip. With regard to its versatility and real-time capability, a field programmable gate array (FPGA) is used to implement the reset management circuit. For the design and implementation of this circuit, the time delays of all involved signal paths are investigated in detail. Measurements prove the functionality of the presented reset management. Furthermore, it is also shown how the reset management influences the dead time of the entire system. Although this work covers a system with three ASICs, the reset management is applicable for other SDD systems using two or more parallelized readout circuits.