Far-ultraviolet and extreme-ultraviolet (FUV/EUV) spectroscopic observations play a crucial role in multiple scientific domains, including solar physics and planetary exosphere studies. This work presents the first implementation of the Micro-channel plate Readout ASIC (MIRA), a 65-nm Application-Specific Integrated Circuit (ASIC) featuring a 32 × 32 pixel array of charge detectors for photon counting applications. We report both standalone performance measurements of MIRA and its characterization when coupled with a Micro-Channel Plate (MCP), demonstrating its feasibility for high-sensitivity detection in FUV/EUV applications. Furthermore, we describe the full-scale redesign of MIRA, transitioning from the initial 32 × 32 array to a more advanced 256 × 256 pixel architecture, featuring a larger detection area. This upgrade addresses critical design challenges, including supply voltage drops due to static current flow, analog front-end optimization for reduced power dissipation, and the implementation of a novel adaptive biasing stage to enhance performance.

Characterization and Redesign of a Modular 65-nm ASIC for Photon Counting with 20 e− Noise

Nassi, L.;Ciavarella-Ciavarella, A.;Carminati, M.;Borghi, G.;Farina, S.;Fiorini, C.
2025-01-01

Abstract

Far-ultraviolet and extreme-ultraviolet (FUV/EUV) spectroscopic observations play a crucial role in multiple scientific domains, including solar physics and planetary exosphere studies. This work presents the first implementation of the Micro-channel plate Readout ASIC (MIRA), a 65-nm Application-Specific Integrated Circuit (ASIC) featuring a 32 × 32 pixel array of charge detectors for photon counting applications. We report both standalone performance measurements of MIRA and its characterization when coupled with a Micro-Channel Plate (MCP), demonstrating its feasibility for high-sensitivity detection in FUV/EUV applications. Furthermore, we describe the full-scale redesign of MIRA, transitioning from the initial 32 × 32 array to a more advanced 256 × 256 pixel architecture, featuring a larger detection area. This upgrade addresses critical design challenges, including supply voltage drops due to static current flow, analog front-end optimization for reduced power dissipation, and the implementation of a novel adaptive biasing stage to enhance performance.
2025
2025 32nd IEEE International Conference on Electronics, Circuits and Systems (ICECS)
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1303965
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