Analog Circuit Design for In-Memory Linear Algebra Accelerators

Since its introduction in 1945, computing systems have been built around von Neumann’s architecture, predicating the physical separation of memory and computing units on grounds of flexibility and generality. However, the increasingly data-driven workloads of modern-day applications exacerbate the energy and latency overheads associated with data shuttling. In-memory computing (IMC) radically subverts the classical paradigm by performing computation in situ within the memory elements, unlocking theoretically unrivaled throughput and energy efficiency. Among the wide spectrum of IMC architectures, closed-loop in-memory computing (CL-IMC) has attracted interest for its capability to accelerate computationally heavy operations of increasing use, such as matrix inversion. This chapter focuses on analog closed-loop circuits for in-memory accelerators. A mathematical framework is derived to develop a matrix-based circuit simulator providing orders-of-magnitude speedups with respect to SPICE solvers. New circuits for the acceleration of regularized regressions and linear quadratic estimation are characterized in terms of accuracy and speed, providing improvement with respect to digital solvers in baseband processing in 6G systems and Kalman filters. Experimental demonstrations finally provide a real-world implementation of CL-IMC topologies. The obtained results strengthen the position of CL-IMC as a promising candidate for next-generation energy-efficient algebraic accelerators.