Design of a Sub-μA Bias Current, Multi-Stage Comparator with Delayed Positive Feedback for Dynamic Gain Enhancement

In many battery-powered applications, reducing the quiescent current consumption of switching converters is an essential feature that helps extend the battery life time of the device. In this frame, DC/DC converters with variable frequency controls are preferred to reduce switching activity and associated losses. To further enhance efficiency, most of the blocks inside the controller are set to idle mode, except for very few components, such as the output comparator. In this paper, the design of a comparator with sub- μ A bias current is presented. The proper number of preamplifier stages is derived by evaluating gain, delay, and offset. To further enhance the transition speed, a delayed weak-positive feedback comparator is proposed. The proposed structure exploits the delay to operate as a strongarm latch during transients while maintaining stability in normal operation. Finally, the comparator is designed in BCD technology, and its static and dynamic performances are verified with transistor-level simulations.