A Hardware/Software Co-Design Approach for Versal-Based K-means Acceleration

K-means is a pivotal clustering algorithm widely accelerated through specific architectures to mitigate the computational load. Nevertheless, existing solutions lack a comprehensive co-design approach for optimization. By combining AI engines with the reconfigurability of FPGAs, this research focuses on Versal systems and proposes a co-design process that addresses both software algorithm optimization and hardware bottleneck analysis. The proposed accelerator achieves a speedup of up to 21.41× compared to state-of-the-art solutions.