HARDWARE INSTRUCTION-LEVEL SCHEDULING IN PROCESSORS

A processing core for executing threads is provided. The processing core comprises: one or more functional units; a shared register file comprising a plurality of registers, each register of the shared register file being configured to store data for executing any thread; and a multi-thread elaboration unit, MTEU, the MTEU comprising: a control module configured to: receive an indication of a plurality of active threads for a given scheduling window; and receive instructions for each of the plurality of active threads; a context manager module configured to load, for each of the plurality of active threads, data required for executing a next one or more of the instructions into a respective one or more registers of the shared register file; and an instruction scheduler module configured to schedule the instructions of the active threads for execution based on availability of the one or more functional units.