FCD Chipkill Solutions for CXL devices

In some implementations, a memory system controller may receive a data block that is associated with a first codeword having a first data portion and a first parity portion, and a second codeword having a second data portion, a second parity portion, and a metadata portion. The memory system controller may detect and correct one or more errors at one or more symbol locations in the first codeword using information in the first codeword. The memory system controller may set one or more erasure conditions at one or more symbol locations in the second codeword that share a positional relationship with the one or more symbol locations in the first codeword having the one or more errors. The memory system controller may correct the one or more erasure conditions at the one or more symbol locations in the second codeword using information in the second codeword.