Rigid image registration is pivotal in modern imaging for correcting distortions of images acquired with different modalities or at different time instants. Literature accelerates its main compute-intensive steps, image transformation and similarity metric computation, through GPUs or FPGAs to meet performance-efficiency constraints. However, GPUs lack energy efficiency while FPGAs lack performance for image transformation. Therefore, we adopt a single heterogeneous system through PEGASO, a methodology and its implementation to co-design the image transformation algorithm on Versal system. We maximize performance by combining custom data layout and hardware optimizations, attaining a 19x speedup over the best GPU-based transformation accelerator. When integrated with FPGA-based similarity metric, PEGASO achieves 82.73x and 20.73x speedup against FPGA- and GPU-based solutions while improving the corresponding energy efficiency of 318.18x and 52.62x.

Co-Designing a 3D Transformation Accelerator for Versal-Based Image Registration

Galfano, Paolo Salvatore;Sorrentino, Giuseppe;D'Arnese, Eleonora;Conficconi, Davide
2024-01-01

Abstract

Rigid image registration is pivotal in modern imaging for correcting distortions of images acquired with different modalities or at different time instants. Literature accelerates its main compute-intensive steps, image transformation and similarity metric computation, through GPUs or FPGAs to meet performance-efficiency constraints. However, GPUs lack energy efficiency while FPGAs lack performance for image transformation. Therefore, we adopt a single heterogeneous system through PEGASO, a methodology and its implementation to co-design the image transformation algorithm on Versal system. We maximize performance by combining custom data layout and hardware optimizations, attaining a 19x speedup over the best GPU-based transformation accelerator. When integrated with FPGA-based similarity metric, PEGASO achieves 82.73x and 20.73x speedup against FPGA- and GPU-based solutions while improving the corresponding energy efficiency of 318.18x and 52.62x.
2024
Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
AI Engine
Data Layout
Transformation
Versal
File in questo prodotto:
File Dimensione Formato  
VersalTransform_ICCD24.pdf

accesso aperto

: Post-Print (DRAFT o Author’s Accepted Manuscript-AAM)
Dimensione 526.21 kB
Formato Adobe PDF
526.21 kB Adobe PDF Visualizza/Apri

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1288454
Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 3
  • ???jsp.display-item.citation.isi??? 2
social impact