We present a fully integrated CMOS architecture performing real-time reconfiguration of free-space optical receivers built in CMOS-compatible Silicon Photonics platforms. The chip comprises 8 independent channels and is used to dynamically drive the thermal actuators that set the working point of a photonic integrated circuit. Each channel includes the readout of a photodetector with 120 dB dynamic range, a digital processor implementing two integral controllers, and two 12-bit DACs driving the actuators. By connecting a pair of ASICs to the photonic chip, we controlled a binary-tree mesh of 15 Mach-Zehnder Interferometers while dissipating approx 10 mW/channel. Our setup achieved a settling time of the receiver ≤q 10 ms when starting from a random working point, and compensated for atmospheric turbulence up to approx 300 Hz. This architecture thus provides a scalable solution for establishing reliable free-space optical links between photonic processors of growing complexity.

CMOS Controller for Real-Time Stabilization and Configuration of Silicon Photonics Free-Space Receivers

Sacchi, Emanuele;Zanetto, Francesco;Martinez Rojas, Andres Ivan;SeyedinNavadeh, SeyedMohammad;Morichetti, Francesco;Melloni, Andrea;Sampietro, Marco;Ferrari, Giorgio
2024-01-01

Abstract

We present a fully integrated CMOS architecture performing real-time reconfiguration of free-space optical receivers built in CMOS-compatible Silicon Photonics platforms. The chip comprises 8 independent channels and is used to dynamically drive the thermal actuators that set the working point of a photonic integrated circuit. Each channel includes the readout of a photodetector with 120 dB dynamic range, a digital processor implementing two integral controllers, and two 12-bit DACs driving the actuators. By connecting a pair of ASICs to the photonic chip, we controlled a binary-tree mesh of 15 Mach-Zehnder Interferometers while dissipating approx 10 mW/channel. Our setup achieved a settling time of the receiver ≤q 10 ms when starting from a random working point, and compensated for atmospheric turbulence up to approx 300 Hz. This architecture thus provides a scalable solution for establishing reliable free-space optical links between photonic processors of growing complexity.
2024
31st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2024
9798350377200
ASIC
CMOS
Free-Space Optics
Silicon Photonics
Wireless Communication
File in questo prodotto:
File Dimensione Formato  
icecs_iris_compressed.pdf

embargo fino al 01/01/2026

: Post-Print (DRAFT o Author’s Accepted Manuscript-AAM)
Dimensione 524.76 kB
Formato Adobe PDF
524.76 kB Adobe PDF   Visualizza/Apri

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1285691
Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus ND
  • ???jsp.display-item.citation.isi??? ND
social impact