Charge-Domain Implementation of a Neural Network in an Analog Integrated Circuit

We propose an analog Neural Network ASIC where computations are implemented in 0.35-µm CMOS technology. A programmable, switched capacitor (SC)-based matrix stores the network weights and executes on-chip the multiply-and-accumulate (MAC) operations needed for the network inference step, with an estimated energy efficiency of ∼ 1.86 TOPs/W. An off-line training phase is performed to emulate the operation of the NN executed in a CMOS process and extract the network parameters. A preliminary schematic simulation of the neuromorphic ASIC has been made to perform an inference step. The chip is designed to be used for in-sensor position sensitivity purposes in Anger Cameras for emission tomography, but it may result of wider interest also for other radiation detector applications leveraging neural networks.