Many high precision measurements of time intervals employ Time-of-Flight (ToF) or Time-Correlate Single-Photon Counting (TCSPC) techniques, exploiting SPAD detectors to reveal single photons with high temporal precision. This work focuses on the design of a Time-to-Digital Converter (TDC) based on a Voltage-Controlled Gated-Ring-Oscillator (GRO). In particular, it presents high-performance in terms of resolution (31.5 ps LSB, Least Significant Bit) and Full-Scale Range (2 μs FSR), allowing a wide range of applications from Light Detection and Ranging (LiDAR) to Fluorescent Imaging (FLIM). The stability of the TDC to Process, Temperature and Voltage (PVT) variations is assessed through a Phase-Locked-Loop (PLL) providing the control voltage to the GRO. In a SPAD array a single global PLL can be implemented, feeding the in-pixel GROs, which experience approximately the same PVT variations. Post-layout simulations are carried out to disclose, before fabrication, the main challenging design trade-offs, from jitter of the converter to PLL stability and noise. The chip design was realized in a 40 nm CMOS technology.
High-Resolution, Long-Range Time-to-Digital Converter for SPAD-Based Time-Correlated Single Photon Counting Applications
Nonne C.;Madonini F.;Villa F.
2023-01-01
Abstract
Many high precision measurements of time intervals employ Time-of-Flight (ToF) or Time-Correlate Single-Photon Counting (TCSPC) techniques, exploiting SPAD detectors to reveal single photons with high temporal precision. This work focuses on the design of a Time-to-Digital Converter (TDC) based on a Voltage-Controlled Gated-Ring-Oscillator (GRO). In particular, it presents high-performance in terms of resolution (31.5 ps LSB, Least Significant Bit) and Full-Scale Range (2 μs FSR), allowing a wide range of applications from Light Detection and Ranging (LiDAR) to Fluorescent Imaging (FLIM). The stability of the TDC to Process, Temperature and Voltage (PVT) variations is assessed through a Phase-Locked-Loop (PLL) providing the control voltage to the GRO. In a SPAD array a single global PLL can be implemented, feeding the in-pixel GROs, which experience approximately the same PVT variations. Post-layout simulations are carried out to disclose, before fabrication, the main challenging design trade-offs, from jitter of the converter to PLL stability and noise. The chip design was realized in a 40 nm CMOS technology.File | Dimensione | Formato | |
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