In-memory computing (IMC) shows a disruptive potential for accelerating artificial intelligence (AI) in both inference and training tasks. Scalable IMC, however, requires novel memory technologies with extremely low current. Here we demonstrate ultra-low current matrix-vector multiplication (MVM) in a crosspoint array of phase change memory (PCM) and ovonic threshold switch (OTS) with one-selector/one-resistor (1S1R) structure operated in the subthreshold regime. Thanks to highly-uniform sub-mu A currents, the 1S1R PCM crosspoint array rejects parasitic IR drop across wires, enabling excellent scaling compared to other memory devices. Our simulation of a fully-connected neural network (FCNN) with ternary weights indicates an accuracy of 98% for MNIST classification with an array size of 512x512, which strongly supports subthreshold-operated 1S1R crosspoint arrays for neural network inference accelerators.

In-memory neural network accelerator based on phase change memory (PCM) with one-selector/one-resistor (1S1R) structure operated in the subthreshold regime

Lepri, N;Mannocci, P;Ielmini, D
2023-01-01

Abstract

In-memory computing (IMC) shows a disruptive potential for accelerating artificial intelligence (AI) in both inference and training tasks. Scalable IMC, however, requires novel memory technologies with extremely low current. Here we demonstrate ultra-low current matrix-vector multiplication (MVM) in a crosspoint array of phase change memory (PCM) and ovonic threshold switch (OTS) with one-selector/one-resistor (1S1R) structure operated in the subthreshold regime. Thanks to highly-uniform sub-mu A currents, the 1S1R PCM crosspoint array rejects parasitic IR drop across wires, enabling excellent scaling compared to other memory devices. Our simulation of a fully-connected neural network (FCNN) with ternary weights indicates an accuracy of 98% for MNIST classification with an array size of 512x512, which strongly supports subthreshold-operated 1S1R crosspoint arrays for neural network inference accelerators.
2023
2023 IEEE International Memory Workshop (IMW)
978-1-6654-7459-7
Deep learning
in-memory computing
neural network accelerator
phase change memory
selector device
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1248538
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