An Application Specific Integrated Circuit (ASIC), called RIGEL, designed for the sparse readout of a Silicon Pixel Drift Detector (PixDD) for space applications is presented. The low leakage current (less than 1 pA at +20 degrees C) and anode capacitance (less than 40 fF) of each pixel (300 mu m x 300 mu m) of the detector, combined with a low-noise electronics readout, allow to reach a high spectroscopic resolution performance even at room temperature. The RIGEL ASIC front-end architecture is composed by a 2-D matrix of 128 readout pixel cells (RPCs), arranged to host, in a 300 mu m-sided square area, a central octagonal pad (for the PixDD anode bump-bonding), and the full-analog processing chain, providing a full-shaped and stretched signal. In the chip periphery, the back-end electronics features 16 integrated 10-bits Wilkinson ADCs, the configuration register and a trigger management circuit. The characterization of a single RPC has been carried out whose features are: eight selectable peaking times from 0.5 mu s to 5 mu s, an input charge range equivalent to 30 keV, and a power consumption of less than 550 mu W per channel. The RPC has been tested also with a 4x4 prototype PixDD and 167 eV Full Width at Half Maximum (FWHM) at the 5.9 keV line of Fe-55 at 0 degrees C and 1.8 mu s of peaking time has been measured.
The sparse readout RIGEL Application Specific Integrated Circuit for Pixel Silicon Drift Detectors in soft X-ray imaging space applications
Massimo Gandola;Filippo Mele;Irisa Dedolli;Piero Malcovati;Giuseppe Bertuccio
2022-01-01
Abstract
An Application Specific Integrated Circuit (ASIC), called RIGEL, designed for the sparse readout of a Silicon Pixel Drift Detector (PixDD) for space applications is presented. The low leakage current (less than 1 pA at +20 degrees C) and anode capacitance (less than 40 fF) of each pixel (300 mu m x 300 mu m) of the detector, combined with a low-noise electronics readout, allow to reach a high spectroscopic resolution performance even at room temperature. The RIGEL ASIC front-end architecture is composed by a 2-D matrix of 128 readout pixel cells (RPCs), arranged to host, in a 300 mu m-sided square area, a central octagonal pad (for the PixDD anode bump-bonding), and the full-analog processing chain, providing a full-shaped and stretched signal. In the chip periphery, the back-end electronics features 16 integrated 10-bits Wilkinson ADCs, the configuration register and a trigger management circuit. The characterization of a single RPC has been carried out whose features are: eight selectable peaking times from 0.5 mu s to 5 mu s, an input charge range equivalent to 30 keV, and a power consumption of less than 550 mu W per channel. The RPC has been tested also with a 4x4 prototype PixDD and 167 eV Full Width at Half Maximum (FWHM) at the 5.9 keV line of Fe-55 at 0 degrees C and 1.8 mu s of peaking time has been measured.File | Dimensione | Formato | |
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