In-memory computing (IMC) is gaining momentum as the most promising candidate for the upcoming non-vonNeumann, machine learning-optimized computing paradigm. Its intrinsic parallelism is well-suited to accelerate matrix-vector multiplications (MVM), which prove challenging for traditional architectures and are a fundamental operation in principal component analysis (PCA), one of the most renowned algorithms for data classification. Here, we show an experimental demonstration of a novel, IMC-based PCA algorithm by inmemory power iteration and deflation executed in a 4-kbit array of resistive random-access memory (RRAM). Our algorithm achieves 95.25% classification accuracy on the Wisconsin Diagnostic Breast Cancer dataset, matching closely results of a floating-point machine while providing a 250× improvement in energy efficiency.

Experimental verification and benchmark of in-memory principal component analysis by crosspoint arrays of resistive switching memory

Mannocci, Piergiulio;Zambelli, Cristian;Ielmini, Daniele
2022-01-01

Abstract

In-memory computing (IMC) is gaining momentum as the most promising candidate for the upcoming non-vonNeumann, machine learning-optimized computing paradigm. Its intrinsic parallelism is well-suited to accelerate matrix-vector multiplications (MVM), which prove challenging for traditional architectures and are a fundamental operation in principal component analysis (PCA), one of the most renowned algorithms for data classification. Here, we show an experimental demonstration of a novel, IMC-based PCA algorithm by inmemory power iteration and deflation executed in a 4-kbit array of resistive random-access memory (RRAM). Our algorithm achieves 95.25% classification accuracy on the Wisconsin Diagnostic Breast Cancer dataset, matching closely results of a floating-point machine while providing a 250× improvement in energy efficiency.
2022
IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022
978-1-6654-8485-5
in-memory computing, resistive random access memory, hardware accelerator, principal component analysis
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1226615
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