A Novel Common-Gate Comparator with Auto-Zeroing Offset Cancellation

This paper presents a novel auto-zeroing common-gate comparator. This topology cancels the input-referred offset voltage by AC coupling the gates of the two input mosfets. The circuit operation is divided in two phases: in the first one, the circuit is in closed loop and samples the offset voltage as a voltage difference between two capacitors, while, in the second phase, the circuit is configured in open loop to compare the two input signals. Monte Carlo simulations run on a reference design in CMOS process shows that the offset standard deviation is reduced from 4.42mV down to 25.85 mu V. The designed comparator shows a 290 mu W power consumption from a 5V supply, while occupying a total area of 0.0156mm(2).