SPAD Pixel with Sub-NS Dead-Time for High-Count Rate Applications

Single-photon avalanche diode (SPAD) exploitation in high-flux applications is often hindered by the trade-off between the SPAD dead-time and afterpulsing probability. In this paper, we present the architecture and the experimental characterization of two chips including a novel SPAD sensing, and readout scheme designed to minimize dead-time (1.78 ns and 0.93 ns respectively) and afterpulsing probability (0.14% maximum). We have coupled this architecture with high-performance SPADs obtaining an extremely stable dead-time (6.44 psrms jitter) that can be easily regulated through an external voltage. Thanks to its compact size, this novel pixel architecture can be easily integrated within high-resolution SPAD arrays for GHz applications.