Low‐leakage zero‐static power consumption analogue CMOS switch

The architecture of a low-leakage switch in complementary metal-oxide-semiconductor (CMOS) technology developed to implement long-term analogue memories for low-power applications is presented. The switch reduces the leakage current using a cascade of modified pass-transistors without active circuits, thus producing a negligible power consumption. The technique is simple, modular, robust, and reduces the leakage current down to tens of aA at room temperature using a TSMC 0.18 µm technology.