As RF transceivers move into the mm-wave frequency range, one of the key issues faced in the design of frequency synthesizers is that, to ensure proper operation of the phase detector, the PLL output frequency has to be scaled down before being compared with the low-frequency reference signal [1]. In this scenario, a key block is the high frequency digital prescaler, often implemented at the expense of large power consumption. As an alternative, injection-locked frequency dividers (ILFDs) are attracting increasing interest, thanks to their low-power and low-phase-noise performance at high frequencies. However, the ILFD locking range decreases with the division factor as higher-order intermixing processes are involved. Moreover, the adoption of small scale CMOS technologies, though enabling higher operating frequency, mitigate transistor nonlinearities thus lowering the achievable intermixing-gain. In this frame, pushing the design of high-order ILFD beyond 20GHz with sufficient locking range is highly challenging. In this work, a novel concurrent operation of tail and direct injectors into a ring-type ILFD by five is exploited for the first time to increase the injection efficiency and the resulting locking range for the same power consumption. A prototype ring-type 28nm-CMOS ILFD by five has been realized in a 28nm CMOS technology achieving the unprecedented performance of >20% locking range over 13.6-69.1GHz with 5.6mW maximum power consumption, and operation up to 100GHz with a 2.6% locking range. The circuit achieves the highest locking range among ILFDs by five at same frequency, and the highest operation frequency.

A 13.6-69.1GHz 5.6mW Ring-Type Injection-Locked Frequency Divider by Five with >20% Continuous Locking Range and Operation up to 101.6GHz in 28nm CMOS

Andrea Leonardo Lacaita;Salvatore Levantino
2021

Abstract

As RF transceivers move into the mm-wave frequency range, one of the key issues faced in the design of frequency synthesizers is that, to ensure proper operation of the phase detector, the PLL output frequency has to be scaled down before being compared with the low-frequency reference signal [1]. In this scenario, a key block is the high frequency digital prescaler, often implemented at the expense of large power consumption. As an alternative, injection-locked frequency dividers (ILFDs) are attracting increasing interest, thanks to their low-power and low-phase-noise performance at high frequencies. However, the ILFD locking range decreases with the division factor as higher-order intermixing processes are involved. Moreover, the adoption of small scale CMOS technologies, though enabling higher operating frequency, mitigate transistor nonlinearities thus lowering the achievable intermixing-gain. In this frame, pushing the design of high-order ILFD beyond 20GHz with sufficient locking range is highly challenging. In this work, a novel concurrent operation of tail and direct injectors into a ring-type ILFD by five is exploited for the first time to increase the injection efficiency and the resulting locking range for the same power consumption. A prototype ring-type 28nm-CMOS ILFD by five has been realized in a 28nm CMOS technology achieving the unprecedented performance of >20% locking range over 13.6-69.1GHz with 5.6mW maximum power consumption, and operation up to 100GHz with a 2.6% locking range. The circuit achieves the highest locking range among ILFDs by five at same frequency, and the highest operation frequency.
Proceedings of the Custom Integrated Circuits Conference IEEE CICC 2021
978-172817581-2
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/1180528
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