Pearson correlation coefficient acceleration for modeling and mapping of neural interconnections

Thanks to the availability of new biomedical technologies and analysis methodologies, the quality of clinical exams and medical research is increasing. These improvements have given the opportunity to analyze large amount of data with an higher level of accuracy. Therefore, processors able to handle compute intensive algorithms and large datasets are needed, and the use of homogeneous processors is becoming inefficient for this purpose. As a result, heterogeneous architectures are becoming the key technology to improve the efficiency of these computations, by allowing a concurrent elaboration of data. In this work, it is proposed a Field Programmable Gate Array (FPGA) implementation of the Pearson Correlation Coefficient (PCC) algorithm, applied to a Brain Network (BN) case study. Itwill be shown that the proposed implementation can achieve up to 10x speedup with respect to a single-threaded Central Processing Unit (CPU) implementation, while guaranteeing 2x performance per Watt ratio in comparison to a Graphic Processing Unit (GPU) implementation. These considerations open to the possibility of using FPGA architectures in application fields, such as data centers and biomedical embedded systems, where power capping and heat are relevant issues to be considered.