We propose a CMOS architecture for spiking neural networks with permanent memory and online learning. It uses a three-transistors synapse with a floating node that stores the synaptic weight, programmed by using only Fowler-Nordheim tunneling current in the pA range for ultra-low power operation. A neuron with a conditioning circuit programs the floating gate synapse following the spike timing dependent plasticity rule. Simulations using a standard 150 nm CMOS process show the online learning capabilities of the architecture.

Tunneling-based CMOS Floating Gate Synapse for Low Power Spike Timing Dependent Plasticity

Mastella M.;Toso F.;Sciortino G.;Prati E.;Ferrari G.
2020

Abstract

We propose a CMOS architecture for spiking neural networks with permanent memory and online learning. It uses a three-transistors synapse with a floating node that stores the synaptic weight, programmed by using only Fowler-Nordheim tunneling current in the pA range for ultra-low power operation. A neuron with a conditioning circuit programs the floating gate synapse following the spike timing dependent plasticity rule. Simulations using a standard 150 nm CMOS process show the online learning capabilities of the architecture.
Proceedings - 2020 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2020
978-1-7281-4922-6
floating gate
spiking
STDP
synapse
VLSI
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/1143256
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