We propose a CMOS architecture for spiking neural networks with permanent memory and online learning. It uses a three-transistors synapse with a floating node that stores the synaptic weight, programmed by using only Fowler-Nordheim tunneling current in the pA range for ultra-low power operation. A neuron with a conditioning circuit programs the floating gate synapse following the spike timing dependent plasticity rule. Simulations using a standard 150 nm CMOS process show the online learning capabilities of the architecture.
Titolo: | Tunneling-based CMOS Floating Gate Synapse for Low Power Spike Timing Dependent Plasticity | |
Autori: | ||
Data di pubblicazione: | 2020 | |
Handle: | http://hdl.handle.net/11311/1143256 | |
ISBN: | 978-1-7281-4922-6 | |
Appare nelle tipologie: | 04.1 Contributo in Atti di convegno |
File in questo prodotto:
File | Descrizione | Tipologia | Licenza | |
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AICAS_2020___Paper final.pdf | Final manuscript | Post-Print (DRAFT o Author’s Accepted Manuscript-AAM) | Accesso apertoVisualizza/Apri |
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