The paper focuses on the theoretical design of a fast analog pulse processing (APP) solution implemented in an ASIC for X-ray spectroscopy. In particular, the APP is cascaded to the front-end combination of silicon drift detectors (SDDs) with state-of-the-art CMOS charge sensitive preamplifiers (CSAs). The limitations of APP are assessed in terms of energy resolution, spectrum quality, and high-throughput capability. The study has been conducted for the systematic assessment of: (i) analysis of the shaping amplifier, considering series noise, ballistic deficit immunity, and pile up immunity; (ii) detector optimization, to minimize the ballistic deficit effect; (iii) analysis of analog-based pile up rejection (PUR) strategies; and (iv) maximum throughput estimation taking into account the chosen specifications of the analog processing channel. Theoretical and simulation findings are complemented by the experimental results achieved with an APP demonstrator, which are also compared to the corresponding ones obtained from a standard digital pulse processor (DPP), showing the competitiveness (in addition to scalability) of APP.

Assessment of analog pulse processor performance for ultra high-rate x-ray spectroscopy

I. Hafizh;M. Carminati;C. Fiorini
2019-01-01

Abstract

The paper focuses on the theoretical design of a fast analog pulse processing (APP) solution implemented in an ASIC for X-ray spectroscopy. In particular, the APP is cascaded to the front-end combination of silicon drift detectors (SDDs) with state-of-the-art CMOS charge sensitive preamplifiers (CSAs). The limitations of APP are assessed in terms of energy resolution, spectrum quality, and high-throughput capability. The study has been conducted for the systematic assessment of: (i) analysis of the shaping amplifier, considering series noise, ballistic deficit immunity, and pile up immunity; (ii) detector optimization, to minimize the ballistic deficit effect; (iii) analysis of analog-based pile up rejection (PUR) strategies; and (iv) maximum throughput estimation taking into account the chosen specifications of the analog processing channel. Theoretical and simulation findings are complemented by the experimental results achieved with an APP demonstrator, which are also compared to the corresponding ones obtained from a standard digital pulse processor (DPP), showing the competitiveness (in addition to scalability) of APP.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1117850
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