The extreme integration levels reached by the silicon manufacturing process allowed the design of high-performance multi-core processors that meet the ever-increasing requirements of software applications. Unfortunately, we are living in the post Dennard’ scaling era, which is characterized by an increasing on-chip power density. This is pushing the problem of dissipating the heat generated by the processor up the next level: the current MOSFET geometry is decreasing the reliability of silicon devices, i.e., it is making them increasingly susceptible to thermal stress and manufacturing defects. In turn, this leads to computing devices that are more likely to experience faults and performance variability issues. To prevent, mitigate, and compensate the aforementioned undesired behaviors, modern systems must rely on a sophisticated run-time support. In this section, we detail how it is done by the HARPA-OS.

The HARPA-OS

Simone Libutti;Giuseppe Massari;William Fornaciari
2019-01-01

Abstract

The extreme integration levels reached by the silicon manufacturing process allowed the design of high-performance multi-core processors that meet the ever-increasing requirements of software applications. Unfortunately, we are living in the post Dennard’ scaling era, which is characterized by an increasing on-chip power density. This is pushing the problem of dissipating the heat generated by the processor up the next level: the current MOSFET geometry is decreasing the reliability of silicon devices, i.e., it is making them increasingly susceptible to thermal stress and manufacturing defects. In turn, this leads to computing devices that are more likely to experience faults and performance variability issues. To prevent, mitigate, and compensate the aforementioned undesired behaviors, modern systems must rely on a sophisticated run-time support. In this section, we detail how it is done by the HARPA-OS.
2019
Harnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms
978-3-319-91961-4
978-3-319-91962-1
Multi many cores, run time management, power optimizaton, HPC
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1066939
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