Despite the remarkable improvements in the effectiveness of High Level Synthesis tools for FPGA development in recent years, they still require some domain specific knowledge and expertise to be used effectively. In this paper we present OXiGen, a tool which aims to further increase the accessibility of HLS technology by harnessing the flexibility of LLVM to offer a high level language front-end for the design of dataflow applications on FPGA. In contrast to many HLS tools, which intend to be general in the architectural templates they offer, OXiGen specifically targets the dataflow computational paradigm, which has proven to be very effective when implemented on FPGA. Starting from a high level language supported by LLVM, the tool generates a dataflow intermediate representation of the target function and translates it into a chosen target language suitable for hardware synthesis. The bitstream generation is handled by a back-end synthesis tool of choice which supports the dataflow computational paradigm. We present an example of this approach targeting MaxCompiler and translating high level computational kernels written in C into MaxJ. OXiGen also provides a resources and performance model for design space exploration purposes, which allows the user to find the optimal translation configuration to optimize the design according to its critical resources and performance goals.

OXiGen: A tool for automatic acceleration of c functions into dataflow FPGA-based kernels

PEVERELLI, FRANCESCO;Rabozzi, Marco;Del Sozzo, Emanuele;Santambrogio, Marco D.
2018-01-01

Abstract

Despite the remarkable improvements in the effectiveness of High Level Synthesis tools for FPGA development in recent years, they still require some domain specific knowledge and expertise to be used effectively. In this paper we present OXiGen, a tool which aims to further increase the accessibility of HLS technology by harnessing the flexibility of LLVM to offer a high level language front-end for the design of dataflow applications on FPGA. In contrast to many HLS tools, which intend to be general in the architectural templates they offer, OXiGen specifically targets the dataflow computational paradigm, which has proven to be very effective when implemented on FPGA. Starting from a high level language supported by LLVM, the tool generates a dataflow intermediate representation of the target function and translates it into a chosen target language suitable for hardware synthesis. The bitstream generation is handled by a back-end synthesis tool of choice which supports the dataflow computational paradigm. We present an example of this approach targeting MaxCompiler and translating high level computational kernels written in C into MaxJ. OXiGen also provides a resources and performance model for design space exploration purposes, which allows the user to find the optimal translation configuration to optimize the design according to its critical resources and performance goals.
2018
Proceedings - 2018 IEEE 32nd International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2018
9781538655559
Dataflow; Design Space Exploration; FPGA; High Level Synthesis; LLVM; Performance Estimation; Resource Estimation; Artificial Intelligence; Computer Networks and Communications; Hardware and Architecture; Information Systems and Management
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1061031
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