Digital PLLs exploit CMOS scaling and allow accurate cancellation of fractional spurs and automatic bandwidth control. In Bang-Bang DPLLs assisted by DTC, performance is only limited by DCO and DTC resolution. Bang-Bang DPLLs assisted by DTC allow same phase-noise performance and fractional spur level as standard DPLLs at much lower power consumption.
Digital phase-locked loops
Levantino, Salvatore
2018-01-01
Abstract
Digital PLLs exploit CMOS scaling and allow accurate cancellation of fractional spurs and automatic bandwidth control. In Bang-Bang DPLLs assisted by DTC, performance is only limited by DCO and DTC resolution. Bang-Bang DPLLs assisted by DTC allow same phase-noise performance and fractional spur level as standard DPLLs at much lower power consumption.File in questo prodotto:
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Levantino_Digital_PLLs_final.pdf
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