FPGA Implementation and Performance of Joint Crest Factor Reduction and Adaptive Predistortion

Non-linear distortion caused by power amplifliers is one of the impairments that limit the performance of digital transmission systems. The detrimental effects of non-linear distortion can be mitigated by predistortion. However, since the peak output power of the amplifier is constrained, one has to accept a compromise between output power and distortion. One method to put the compromise under control is that of reducing the crest factor of the signal before predistortion, taking the crest-limited signal as a desired output signal. In this paper, we present experimental results obtained by a system implemented on FPGA that consists of the cascade of crest factor reduction, adaptive predistortion and a synthetic memoryless model of the power amplifier. The results show that, with a Gaussian input signal, crest factor reduction is the key parameter that allows to optimize the trade-off between output power and signal distortion. Also, the results show that our implementation achieves virtually optimal performance with moderate use of FPGA resources.