Rapid prototyping and FPGA-in-the-loop verification of a DFrFT-based OFDM system

Orthogonal frequency division multiplexing (OFDM) based on the use of discrete fractional Fourier transform (DFrFT) has recently gained interest due to its lower sensitivity to synchronization errors in comparison with conventional OFDM based on the use of the discrete Fourier transform (DFT). Although this higher robustness to synchronization errors is a well-recognized fact, only few works are available in the literature that concern with DFrFT hardware implementation. In this work, we consider its implementation in a Field Programmable Gate Array (FPGA). To verify the design of the DFrFT-based OFDM system, we use FPGA-in-the-Loop (FIL) co-simulation method to evaluate bit error rate (BER) in presence of carrier frequency offset (CFO) when transmission takes place over a frequency selective Rayleigh fading channel.