Lock-In Amplifier Architectures for Sub-ppm Resolution Measurements

Ideally, lock-in amplifiers (LIAs) would be able to measure a minimum signal variation limited by the noise of the front-end amplifier and the filtering bandwidth. On the contrary, a detailed characterization of digital LIAs shows an unforeseen 1/f noise at the instruments demodulated output, proportional to the total signal amplitude. The signal-proportionality and 1/f nature of the measured noise pose a fundamental limit to the LIAs achievable resolution. This limit has been found to be dependent from the instrument maximum operating frequency, from few ppm for LIAs operating up to few hundreds of kHz, to few tens of ppm for LIAs operating up to few MHz or tens of MHz. The additional noise is due to slow gain fluctuations that the signal experiences from the generation stage to the acquisition one. To compensate them, a switched ratiometric technique based on two ADCs alternately acquiring the signal coming from the device under test and the stimulus signal has been conceived. The idea is that both signals should experience the same gain fluctuations, which can be successively removed by means of a division on the outputs of the synchronous demodulation. An FPGA-based LIA working up to 10 MHz and implementing the technique has been realized and results demonstrate a resolution improvement of more than an order of magnitude compared to standard implementations working up to similar frequencies (from tens of ppm down to sub-ppm values).