Comparison of interpolation techniques for TDCs implementation in FPGA

The Tapped Delay Line Time-to-Digital Converter (TDL TDC) architectures implemented into FPGA devices suffer the penalty of high differential and integral non-linearity errors that hardly can limit the resolution unless interpolation and calibration procedures are also implemented. Aim of this contribution is to make clear the need of the interpolation and calibration and the definition of a guideline to choose the interpolation technique most suited to the technological characteristics of the FPGA device.